Essential components of field effect transistors include a gate structure and source and drain regions on opposite sides of the gate structure. As is well known, the voltage applied to the gate structure controls the current flow between the source and drain regions which are doped and formed by, e.g., ion implantation. In metal oxide field effect transistors (MOSFET), the gate is separated from the current channel by a thin oxide layer.
As device dimensions shrank from those used in the early MOSFET devices, effects that were unimportant with the early devices became important and the basic structure described had to be modified to obtain the desired device characteristics. For example, the conventional MOSFET structure has a relatively large electric field near the portion of the gate closest to the source/drain regions. The electric field attracts carriers from the channel and some carriers become trapped in the oxide. Such trapped carriers may lead to, e.g., undesirably large changes in the threshold voltage. As the device dimensions scale down to submicron dimensions, these effects are enhanced. Dividing the source/drain regions into two regions with different dopant concentrations reduces the scope of some of these effects. The region with the lower dopant concentration is nearer the gate structure than is the region with the higher dopant concentration. The structure is called a lightly doped drain and is commonly referred to by the acronym LDD.
The now conventional LDD structure is typically formed with two ion implantation steps; a light, first implant and a heavy, second implant which does not penetrate into the lightly doped regions because of, e.g., oxide sidewalls on the gate structure that are formed after the first implant step. This structure alleviates the effect discussed above with respect to the earlier MOSFET structure which lacked an LDD structure.
However, for channel lengths of approximately 0.6 microns and less, the conventional LDD structure described also begins to exhibit drawbacks. For example, the oxide spacers begin to suffer adverse effects from hot carriers and the S/D resistance, due to the lightly doped region, becomes significant as compared to the channel resistance for channel lengths less than 0.6 .mu.m. Several structures have been proposed to overcome at least some of the drawbacks of the conventional structure by using a gate structure that overlaps at least a portion of the heavily doped source/drain regions, i.e., there is a gate/drain overlap. See, e.g., Izawa et al., International Electron Devices Meeting, pp. 38-41, Washington, D.C., 1987. The device described was termed GOLD which is an acronym for gate-drain overlapped LDD. The structure is formed by using an etching process that leaves a portion of the gate polysilicon overlapping the LDD regions. Another approach to achieving gate/drain overlap is described by Chen et al. in 1990 Symposium on VLSI Technology, pp. 39-40. This approach used polysilicon sidewalls on the gate structure which overlapped the source/drain regions. The authors stated that the use of conducting sidewalls instead of insulating sidewalls was a straightforward method of obtaining the desired gate/drain overlap, but the Si sidewalls were not connected to the transistor gate. That is, the sidewalls are floating electrically and only capacitively coupled to the gate. The structure does not take full advantage of the gate/drain overlap.
Another approach to gate/drain overlap which has received much attention recently is termed the inverse T-gate. See, for example, the papers by Wen et al., pp. 765-768 and Pfiester et al., pp. 769-772, International Electron Devices Meeting, Washington, D.C., 1989. The inverse T-gate structure realizes the gate/drain overlap by using a gate structure having a bottom conducting portion that is wider than the top potion and which overlaps the drain region although it is separated from the drain region by a thin oxide layer. The first paper described two embodiments. The first embodiment is exemplary and will be described briefly here. After the gate oxide is formed, an additional polysilicon layer and another oxide layer are deposited. Polysilicon for the gate is deposited and the gate patterned. These steps are followed by the deposition of another polysilicon layer and a dielectric layer. These layers are etched back to form oxide spacers which have a conductive polysilicon layer between them and the gate oxide layer. The conductive polysilicon overlaps the lightly doped drain. The second paper describes a conceptually similar structure.
None of the methods or structures described are compatible with a self-aligned silicide process, and cannot form a silicide to reduce parasitic resistance without causing a gate to source/drain bridging problem.